The present disclosure relates generally to interconnection networks or advanced networking architectures in large-scale, parallel processing systems and parallel storage systems, and, more particularly, to a quasi-optimized interconnection network for, and a method of, interconnecting a number of processing cores or nodes in such systems to minimize time delay for data communication between such nodes.
It is known to employ a supercomputer having a high-level of computational capacity to minimize processing time for large, intensive calculations in various fields, such as telecommunications, biochemistry, and theoretical physics, among others. These calculations are often performed through the use of large-scale, parallel processing by central processing units (CPUs), whereby multiple calculations are performed simultaneously on multiple independent processor cores, also known as “nodes.” Data must be passed and shared between these nodes for the whole supercomputer to function cohesively. As CPU clock speeds approach the limit imposed by the laws of physics, competitive supercomputers typically add and couple more and more nodes to the interconnection network, and this arrangement or topology of a multitude of nodes, in turn, tends to increase the latency or time delay to initiate data passing between the nodes. A lengthy latency can become a bottleneck for sharing data, thereby degrading supercomputer performance.
Current supercomputers are growing so rapidly in complexity that new and efficient topologies cannot be developed fast enough to keep up with the growth in the number of nodes. In effect, supercomputers, today, are designed with relatively inefficient topologies that have simple, symmetrical, and easy-to-construct designs, such as the known Mesh interconnection network of FIG. 1 in which the nodes are interconnected in multiple rows and columns, or the known Torus interconnection network of FIG. 2. While the Mesh and Torus networks, and their known derivatives, such as the Packed Exponential Connections, the Shifted Recursive Torus, the TESH, the Interlaced Bypass Torus, and the Recursive Diagonal Torus, are easy to construct and have been applied industrially given their simple design, these topologies have proven in practice to he extremely inefficient with regards to the time delay for data communication within large-scale, parallel systems, or other large-scale systems with a multitude of nodes.
Another known interconnection network topology is the Hypercube network of FIG. 3, which is slightly more efficient than the Mesh and Torus networks with regards to the time delay. However, the size or diameter of the Hypercube network grows very quickly as more nodes are added. The diameter is defined as the largest of the distances between all pairs of the nodes. The increased size is also true for the derivatives of the Hypercube network.
The lack of low-latency, low diameter, and high efficiency, interconnection networks available has now become a major challenge in creating massive processing and storage systems in the supercomputing industry, as more effective interconnection networks are needed to make faster, smaller, and more energy-efficient, large-scale, parallel systems.
Accordingly, it would be desirable to more optimally arrange the nodes in a topology that minimizes latency, that minimizes the size of the interconnection network, and that makes the interconnection network more energy-efficient, while still maintaining production feasibility.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and locations of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
The system and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will he readily apparent to those of ordinary skill in the art having the benefit of the description herein.